Performance of Stacked Nanosheets Gate-All-Around and Multi-Gate Thin-Film-Transistors

被引:18
作者
Lin, Yu-Ru [1 ]
Yang, Yi-Yun [1 ]
Lin, Yu-Hsien [2 ]
Kurniawan, Erry Dwi [1 ,3 ,4 ]
Yeh, Mu-Shin [5 ]
Chen, Lun-Chun [1 ,6 ]
Wu, Yung-Chun [1 ]
机构
[1] Natl Tsing Hua Univ, Dept Engn & Syst Sci, Hsinchu 300, Taiwan
[2] Natl United Univ, Dept Elect Engn, Miaoli 36003, Taiwan
[3] Acad Sinica, Taiwan Int Grad Program, Nano Sci & Technol Program, Hsinchu 300, Taiwan
[4] Natl Tsing Hua Univ, Hsinchu 300, Taiwan
[5] Natl Appl Res Labs, Natl Nano Device Labs, Hsinchu 300, Taiwan
[6] eMemory Technol Inc, Business Grp 1, Prod Div 2, Hsinchu 30265, Taiwan
关键词
Thin-film transistor (TFT); gate-all-around (GAA); Nanosheet (NS); stacked structure;
D O I
10.1109/JEDS.2018.2873008
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This comprehensive study of the horizontally p-type stacked nanosheets inversion mode thin-film transistor with gate-all-around (SNS-GAATFT) and multi-gate (SNS- EFT) structures. The stacked nanosheets device structure, fabrication, and electrical characteristics are analyzed. The SNS-GAATFT reveals better performance to multi-gate SNS-TFT. The proposed inversion mode SNS-TFT has properties of the easy process with low cost and compatible with all 3-D Si CMOS and AMOLED applications. Moreover, the SNS-GAAEFT is suitable for future monolithic 3-D IC for 2015's ITRS technology roadmap for the year 2024-2030.
引用
收藏
页码:1187 / 1191
页数:5
相关论文
共 11 条
[1]  
[Anonymous], 2015, TCAD SENT DEV MAN SY
[2]  
[Anonymous], 2015, ITRS ROADMAP VERSION
[3]  
[Anonymous], 2012, P IEEE 11 INT C SOLI
[4]   Sequential Lateral Solidification of Silicon Thin Films on Cu BEOL-Integrated Wafers for Monolithic 3-D Integration [J].
Carta, Fabio ;
Gates, Stephen M. ;
Limanov, Alexander B. ;
Im, James S. ;
Edelstein, Daniel C. ;
Kymissis, Ioannis .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (11) :3887-3891
[5]  
Cheng Y. C., 2014, IEDM, DOI 10.1109/IEDM.2014.7047116
[6]  
Hung-Bin Chen, 2013, 2013 Symposium on VLSI Technology, pT232
[7]   A Vertically Integrated Junctionless Nanowire Transistor [J].
Lee, Byung-Hyun ;
Hur, Jae ;
Kang, Min-Ho ;
Bang, Tewook ;
Ahn, Dae-Chul ;
Lee, Dongil ;
Kim, Kwang-Hee ;
Choi, Yang-Kyu .
NANO LETTERS, 2016, 16 (03) :1840-1847
[8]  
Loubet N, 2017, S VLSI TECH, pT230, DOI 10.23919/VLSIT.2017.7998183
[9]  
Natarajan S., 2014, 2014 IEEE International Electron Devices Meeting (IEDM), DOI 10.1109/IEDM.2014.7046976
[10]  
Yeh M. S., 2014, IEDM, DOI 10.1109/IEDM.2014.7047115