System-Level Modeling and Microprocessor Reliability Analysis for Backend Wearout Mechanisms

被引:0
作者
Chen, Chang-Chih [1 ]
Milor, Linda [1 ]
机构
[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA
来源
DESIGN, AUTOMATION & TEST IN EUROPE | 2013年
基金
美国国家科学基金会;
关键词
Wearout Mechanisms; Microprocessor; Reliability; EM; SIV; SM; TDDB; Aging; LIFETIME; IMPACT;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Backend wearout mechanisms are major reliability concerns for modern microprocessors. In this paper, a framework which contains modules for backend time-dependent dielectric breakdown (BTDDB), electromigration (EM), and stress-induced voiding (SIV) is proposed to analyze circuit layout geometries and interconnects to accurately estimate state-of-art microprocessor lifetime due to each mechanism. Our methodology incorporates the detailed electrical stress, temperature, linewidth and cross-sectional areas of each interconnect within the microprocessor system. We analyze several layouts using our methodology and highlight the lifetime-limiting wearout mechanisms, along with the reliability-critical microprocessor functional units, using standard benchmarks.
引用
收藏
页码:1615 / 1620
页数:6
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