共 21 条
[2]
BRUT H, 1997, P IEEE INT C MICR TE, P188
[5]
Cros A., 2005, ICMTS 2005. Proceedings of the 2005 International Conference on Microelectronic Test Structures (IEEE Cat. No.05CH37622), P69
[6]
Cros A, 2006, INT EL DEVICES MEET, P399
[7]
Fully-depleted SOI technology using high-K and single-metal gate for 32nm node LSTP applications featuring 0.179μm2 6T-SRAM bitcell
[J].
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2,
2007,
:267-+
[9]
ANALYTICAL MODELING OF THE MOS-TRANSISTOR
[J].
PHYSICA STATUS SOLIDI A-APPLIED RESEARCH,
1989, 113 (01)
:223-240
[10]
JOMAAH J, 2005, P ICNF C, P181