A low-voltage low-power CMOS analog adaptive equalizer for UTP-5 cables

被引：22
|
作者：
Fayed, Ayman A. [1 ]
Ismail, Mohammed [1 ]
机构：
[1] Ohio State Univ, Dept Elect Engn, Analog VLSI Lab, Columbus, OH 43210 USA
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2008年 / 55卷 / 02期
关键词：
adaptive equalizers; adaptive filters; CMOS integrated circuits; intersymbol interference (ISI); transceivers;
D O I：
10.1109/TCSI.2008.916440
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An analog adaptive equalizer based on a feed-forward architecture is implemented in 0.18-mu m digital CMOS process. The equalizer is implemented with only digital core devices and operates at 125 Mbps. over Unshielded-Twisted-Pair Category-5 cable of up to 100 in. Novel low-power circuit and system techniques resulted in 3.7-mW total power consumption and supply voltage operation as low as 1.6 V. The maximum peak-to-peak jitter at the output of the equalizer (including the transmit path driver) under all cable length is 0.33 UI. The total area of the equalizer is 27738 mu m(2).
引用
收藏
页码：480 / 495
页数：16
相关论文
共 50 条
  • [1] Low-Voltage Low-Power CMOS Design
    Dokic, Branko L.
    Pesic-Brdanin, Tatjana
    Cavka, Drago
    2016 INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (INDEL), 2016,
  • [2] On the design of low-voltage, low-power CMOS analog multipliers for RF applications
    Debono, CJ
    Maloberti, F
    Micallef, J
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (02) : 168 - 174
  • [3] Design of a CMOS low-power and low-voltage four-quadrant analog multiplier
    Liu, Weihsing
    Liu, Shen-Iuan
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2010, 63 (02) : 307 - 312
  • [4] Design of a CMOS low-power and low-voltage four-quadrant analog multiplier
    Weihsing Liu
    Shen-Iuan Liu
    Analog Integrated Circuits and Signal Processing, 2010, 63 : 307 - 312
  • [5] A low-voltage, low-power CMOS phase shifter
    Ferri, G
    De Laurentiis, P
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2000, 28 (02) : 187 - 191
  • [6] Low-voltage, low-power CMOS delay element
    Seoul Natl Univ, Seoul, Korea, Republic of
    IEEE J Solid State Circuits, 7 (966-971):
  • [7] Low-power and low-voltage CMOS digital design
    Piguet, C
    MICROELECTRONIC ENGINEERING, 1997, 39 (1-4) : 179 - 208
  • [8] A CMOS low-voltage low-power temperature sensor
    Crepaldi, Paulo Cesar
    Pimenta, Tales Cleber
    Moreno, Robson Luiz
    MICROELECTRONICS JOURNAL, 2010, 41 (09) : 594 - 600
  • [9] A low-voltage and low-power CMOS active pixel
    Zhang, M
    Llaser, N
    Devos, F
    CISST'2000: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON IMAGING SCIENCE, SYSTEMS, AND TECHNOLOGY, VOLS I AND II, 2000, : 131 - 136
  • [10] Low-power and low-voltage CMOS digital design
    CSEM Cent Suisse d'Electronique et, de Microtechnique SA, Neuchatel, Switzerland
    Microelectron Eng, 1-4 (179-208):
12345