An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications

被引：45

作者：

Li, Jixuan ^{[1
]}

Un, Ka-Fai ^{[1
]}

Yu, Wei-Han ^{[1
]}

Mak, Pui-In ^{[1
]}

Martins, Rui P. ^{[1
]}

机构：

[1] Univ Macau, Fac Sci & Technol, State Key Lab Analog & Mixed Signal VLSI IME & DE, Macau, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2021年 / 68卷 / 09期

关键词：

Frequency modulation; Kernel; Throughput; Parallel processing; Memory management; Field programmable gate arrays; Computational efficiency; Computation efficiency; convolutional neural network (CNN); FPGA; object recognition; reconfigurability; THROUGHPUT; CNN;

D O I：

10.1109/TCSII.2021.3095283

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The computational efficiency is the prime concern of a computation-intensive deep convolutional neural network (CNN). In this Brief, we report an FPGA-based computation-efficient reconfigurable CNN accelerator. It innovates in the utilization of a kernel partition technique to substantially reduce the repeated access to the input feature maps and the kernels. As a result, it balances the ability for parallel computing while consuming less system power. Experimental results prove that the proposed CNN accelerator achieves a peak throughput of 220.0 GOP/s with an energy efficiency of 22.9 GOPs/W at 151.4 frames/s for the AlexNet. It is also reconfigurable to process VGG-16 befitting complex object recognition.

引用

页码：3143 / 3147

页数：5

共 50 条

[31] Efficient FPGA-Based Convolutional Neural Network Implementation for Edge Computing
Cuong, Pham-Quoc
Thinh, Tran Ngoc
JOURNAL OF ADVANCES IN INFORMATION TECHNOLOGY, 2023, 14 (03) : 479 - 487
[32] An Energy-Efficient Convolutional Neural Network Processor Architecture Based on a Systolic Array
Zhang, Chen
Wang, Xin'an
Yong, Shanshan
Zhang, Yining
Li, Qiuping
Wang, Chenyang
APPLIED SCIENCES-BASEL, 2022, 12 (24):
[33] An FPGA-based Accelerator Implementation for Deep Convolutional Neural Networks
Zhou, Yongmei
Jiang, Jingfei
PROCEEDINGS OF 2015 4TH INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND NETWORK TECHNOLOGY (ICCSNT 2015), 2015, : 829 - 832
[34] FPGA-based Convolutional Neural Network Accelerator design using High Level Synthesize
Ghaffari, Sina
Sharifian, Saeed
2016 2ND INTERNATIONAL CONFERENCE OF SIGNAL PROCESSING AND INTELLIGENT SYSTEMS (ICSPIS), 2016, : 29 - 34
[35] Design framework for an energy-efficient binary convolutional neural network accelerator based on nonvolatile logic
Suzuki, Daisuke
Oka, Takahiro
Tamakoshi, Akira
Takako, Yasuhiro
Hanyu, Takahiro
IEICE NONLINEAR THEORY AND ITS APPLICATIONS, 2021, 12 (04): : 695 - 710
[36] An Energy-Efficient FPGA-based Matrix Multiplier
Tan, Yiyu
Imamura, Toshiyuki
2017 24TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS), 2017, : 514 - 517
[37] A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator
Chen, Xiaobai
Yu, Zhiyi
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 26 (07) : 1408 - 1412
[38] Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional Neural Network
Wang, Maolin
Lee, Kelvin C. M.
Chung, Bob M. F.
Bogaraju, Sharatchandra Varma
Ng, Ho-Cheung
Wong, Justin S. J.
Shum, Ho Cheung
Tsia, Kevin K.
So, Hayden Kwok-Hay
IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS, 2022, 33 (07) : 2853 - 2866
[39] A High-Efficiency FPGA-Based Accelerator for Binarized Neural Network
Guo, Peng
Ma, Hong
Chen, Ruizhi
Wang, Donglin
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2019, 28
[40] An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications
Zhao, Zhongyu
Cao, Rujian
Un, Ka-Fai
Yu, Wei-Han
Mak, Pui-In
Martins, Rui P.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2023, 70 (01) : 281 - 285

← 1 2 3 4 5 →