An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications

被引：45
|
作者：
Li, Jixuan [1 ]
Un, Ka-Fai [1 ]
Yu, Wei-Han [1 ]
Mak, Pui-In [1 ]
Martins, Rui P. [1 ]
机构：
[1] Univ Macau, Fac Sci & Technol, State Key Lab Analog & Mixed Signal VLSI IME & DE, Macau, Peoples R China
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2021年 / 68卷 / 09期
关键词：
Frequency modulation; Kernel; Throughput; Parallel processing; Memory management; Field programmable gate arrays; Computational efficiency; Computation efficiency; convolutional neural network (CNN); FPGA; object recognition; reconfigurability; THROUGHPUT; CNN;
D O I：
10.1109/TCSII.2021.3095283
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The computational efficiency is the prime concern of a computation-intensive deep convolutional neural network (CNN). In this Brief, we report an FPGA-based computation-efficient reconfigurable CNN accelerator. It innovates in the utilization of a kernel partition technique to substantially reduce the repeated access to the input feature maps and the kernels. As a result, it balances the ability for parallel computing while consuming less system power. Experimental results prove that the proposed CNN accelerator achieves a peak throughput of 220.0 GOP/s with an energy efficiency of 22.9 GOPs/W at 151.4 frames/s for the AlexNet. It is also reconfigurable to process VGG-16 befitting complex object recognition.
引用
收藏
页码：3143 / 3147
页数：5
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