An Area-Efficient Temperature Compensated Sub-Threshold CMOS Voltage Reference

被引：0

作者：

Kim, Hyojun ^{[1
]}

Park, Jun-Eun ^{[2
]}

Jeong, Deog-Kyoon ^{[1
]}

机构：

[1] Seoul Natl Univ, Seoul, South Korea

[2] Chungnam Natl Univ, Daejeon, South Korea

来源：

2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020) | 2020年

关键词：

voltage reference; PTAT; CTAT; CMOS; technology scaling;

D O I：

10.1109/ISOCC50952.2020.9333020

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents an area-efficient voltage reference that mitigates the shortcomings of technology scaling. The proposed voltage reference offers temperature coefficient of 34 ppm/degrees C, line sensitivity of 2.88 %/V, with peak-to-peak process variation of 43 mV. The voltage reference operates in supply range from 0.7 V to 1.1 V. By exploiting the minimum possible gate length, it can be implemented in compact area of 0.00016 mm(2).

引用

页码：153 / 154

页数：2

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