Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System

被引：45

作者：

Cho, Minki ^{[1
]}

Liu, Chang ^{[1
]}

Kim, Dae Hyun ^{[1
]}

Lim, Sung Kyu ^{[1
]}

Mukhopadhyay, Saibal ^{[1
]}

机构：

[1] Georgia Inst Technol, Sch Elect & Comp Engn, Atlanta, GA 30332 USA

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2011年 / 1卷 / 11期

基金：

美国国家科学基金会;

关键词：

3-D integrated circuit; signal integrity; test; through-silicon-via;

D O I：

10.1109/TCPMT.2011.2166961

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this paper, we present a methodology for characterization and repair of signal degradation in through-silicon-vias (TSVs) in 3-D integrated circuits (ICs). The proposed structure can detect the signal degradation through TSVs due to resistive shorts in liner oxide and variations in resistance of TSV due to weak open and/or bonding resistance. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery circuit to maintain signal fidelity. This allows electrical repair of TSVs with moderate defects leading to better design yield and system functionality. This paper presents the design of the test and recovery structure and demonstrates their effectiveness through stand alone simulations as well as in a full-chip physical design of a 3-D IC.

引用

页码：1718 / 1727

页数：10

共 17 条

[1]

[Anonymous], Predictive technology model (ptm)

[2]

[Anonymous], 2009, PROC IEEE INT C 3D S

[3]

[Anonymous], 2010, HSPICE

[4] On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification [J].

Chen, Po-Yuan ;

Wu, Cheng-Wen ;

Kwai, Ding-Ming .

2009 ASIAN TEST SYMPOSIUM, PROCEEDINGS, 2009, :450-+

[5] Design Method and Test Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System [J].

Cho, Minki ;

Liu, Chang ;

Kim, Dae Hyun ;

Lim, Sung Kyu ;

Mukhopadhyay, Saibal .

2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), 2010, :694-697

[6]

Dae Hyun Kim, 2009, Proceedings of the 2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2009), P674

[7] Test Challenges for 3D Integrated Circuits [J].

Lee, Hsien-Hsin S. ;

Chakrabarty, Krishnendu .

IEEE DESIGN & TEST OF COMPUTERS, 2009, 26 (05) :26-35

[8]

Lee Y. J., 2010, P ACM INT WORKSH TIM, P19

[9] SOC Test Architecture and Method for 3-D ICs [J].

Lo, Chih-Yen ;

Hsing, Yu-Tsao ;

Denq, Li-Ming ;

Wu, Cheng-Wen .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (10) :1645-1649

[10]

Marinissen Erik Jan, 2009, Proceedings of the 2009 IEEE International Test Conference (ITC 2009), DOI 10.1109/TEST.2009.5355674

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