Study on the Mechanism and Modeling for Super-filling of High-Aspect-Ratio Features with Copper by Catalyst Enhanced Chemical Vapor Deposition Coupled with Plasma Treatment

被引:1
作者
Kim, Chang-Gyu [1 ]
Lee, Do-Seon [1 ]
Lee, Won-Jong [1 ]
机构
[1] Korea Adv Inst Sci & Technol, Dept Mat Sci & Engn, Taejon 305701, South Korea
来源
KOREAN JOURNAL OF METALS AND MATERIALS | 2011年 / 49卷 / 04期
关键词
electrical/electronic materials; vapor deposition; surface; computer simulation; Cu CECVD; 3-DIMENSIONAL CHIP STACKING; CU; TECHNOLOGY;
D O I
10.3365/KJMM.2011.49.4.334
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The mechanism behind super-filling of high-aspect-ratio features with Cu by catalyst-enhanced chemical vapor deposition (CECVD) coupled with plasma treatment is described and the metrology required to predict the filling feasibility is identified and quantified. The reaction probability of a Cu precursor was, determined as a function of substrate temperature. Iodine adatoms are deactivated by the bombardment of energetic particles and also by the overdeposition of sputtered Cu atoms during the plasma treatment. The degree of deactivation of adsorbed iodine was experimentally quantified. The quantified factors, reaction probability and degree of deactivation of iodine were introduced to the simulation for the prediction of the trench filling aspect by CECVD coupled with plasma treatment. Simulated results show excellent agreement with the experimental filling aspects.
引用
收藏
页码:334 / 341
页数:8
相关论文
共 19 条
[1]  
Bird G.A., 1976, MOL GAS DYNAMICS
[2]   3-D topography simulator (3-D MULSS) based on a physical description of material topography [J].
Fujinaga, M ;
Kotani, N .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (02) :226-238
[3]   Surfactant-catalyzed chemical vapor deposition of copper thin films [J].
Hwang, ES ;
Lee, J .
CHEMISTRY OF MATERIALS, 2000, 12 (08) :2076-2081
[4]   Interconnect fabrication by superconformal iodine- catalyzed chemical vapor deposition of copper [J].
Josell, D ;
Kim, S ;
Wheeler, D ;
Moffat, TP ;
Pyo, SG .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2003, 150 (05) :C368-C373
[5]   High Speed Cu Filling Into TSV by Pulsed Current for 3 Dimensional Chip Stacking [J].
Kim, In Rak ;
Park, Jun Kyu ;
Chu, Yong Cheol ;
Jung, Jae Pil .
KOREAN JOURNAL OF METALS AND MATERIALS, 2010, 48 (07) :667-673
[6]   Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection [J].
Knickerbocker, JU ;
Andry, PS ;
Buchwalter, LP ;
Deutsch, A ;
Horton, RR ;
Jenkins, KA ;
Kwark, YH ;
McVicker, G ;
Patel, CS ;
Polastre, RJ ;
Schuster, C ;
Sharma, A ;
Sri-Jayantha, SM ;
Surovic, CW ;
Tsang, CK ;
Webb, BC ;
Wright, SL ;
McKnight, SR ;
Sprogis, EJ ;
Dang, B .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2005, 49 (4-5) :725-753
[7]   High-aspect-ratio copper-via-filling for three-dimensional chip stacking - II. Reduced electrodeposition process time [J].
Kondo, K ;
Yonezawa, T ;
Mikami, D ;
Okubo, T ;
Taguchi, Y ;
Takahashi, K ;
Barkey, DP .
JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2005, 152 (11) :H173-H177
[8]   The Effect of Plasma Treatment on Adsorbed Iodine as a Catalyst in Chemical Vapor Deposition of Copper and Application to Filling of Deep Trenches with High Aspect Ratios [J].
Lee, Do-Seon ;
Lee, Won-Jong .
JAPANESE JOURNAL OF APPLIED PHYSICS, 2009, 48 (07)
[9]  
Lee H. B., 2005, THESIS KAIST DAEJEON
[10]   Enhancement of iodine adsorption on ruthenium glue layer for seedless CECVD of Cu [J].
Lee, HB ;
Kwak, DK ;
Kang, SW .
ELECTROCHEMICAL AND SOLID STATE LETTERS, 2005, 8 (02) :C39-C42