Cost-efficient partially-parallel irregular LDPC decoder with Message Passing schedule

被引：0

作者：

Li, Xing ^{[1
]}

Abe, Yuta ^{[1
]}

Shimizu, Kazunori ^{[1
]}

Qiu, Zhen ^{[1
]}

Ikenaga, Takeshi ^{[1
]}

Goto, Satoshi ^{[1
]}

机构：

[1] Waseda Univ, Grad Sch Informat Prod & Syst, Wakamatsu Ku, Fukuoka 8080135, Japan

来源：

2007 INTERNATIONAL SYMPOSIUM ON INTEGRATED CIRCUITS, VOLS 1 AND 2 | 2007年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper proposes an improved Message Passing schedule for irregular LDPC decoder. Redundant memory accesses and column operations are removed by utilizing the characteristics of partial-parallel irregular LDPC decoding algorithm. As a result, the memory access frequency and hardware cost are efficiently reduced. According to the experimental results and comparison with existing work, proposed decoder provides a 30% hardware area reduction and a 36% power consumption saving with the same error correcting performance.

引用

页码：508 / 511

页数：4

共 8 条

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