Area-Efficient Power-Rail ESD Clamp Circuit With False-Trigger Immunity in 28nm CMOS Process

In this work, a new power-rail electrostatic discharge (ESD) clamp circuit with hybrid trigger mechanism is proposed and implemented in a 28-nm CMOS process. Measurements from silicon chips show that the proposed power clamp circuit is capable of achieving mu s-level transient response time with RC time constant of only 10 ns, thus greatly improving area efficiency. Compared to traditional transient circuit with same response time, the proposed one achieves a trigger circuit (TC) area reduction of over 90%. The proposed circuit achieves strong false-trigger immunity under fast power-on conditions. In addition, the circuit also has low standby leakage current of less than 10 nA at different BigFET widths. To verify the proposed circuit, the simulation and test results are analyzed in detail for this paper.