A Low Noise and Low Power RF Front-End for 5.8-GHz DSRC Receiver in 0.13 μm CMOS

被引：2
|
作者：
Choi, Jaeyi [1 ]
Seo, Shin-Hyouk
Moon, Hyunwon [2 ]
Nam, Ilku
机构：
[1] Pusan Natl Univ, Sch Elect Engn, Dept Elect Engn, Pusan, South Korea
[2] Samsung Elect, Gyeonggi Do, South Korea
来源：
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | 2011年 / 11卷 / 01期
关键词：
CMOS; DSRC; low noise; low power; RF front-end; TRANSCEIVER;
D O I：
10.5573/JSTS.2011.11.1.059
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A low noise and low power RF front-end for 5.8 GHz DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 GHz LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 mu m CMOS process and draws 7.3 mA from a 1.2 V supply voltage. It shows a voltage gain of 40 dB and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.
引用
收藏
页码：59 / 64
页数：6
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