Crosstalk analysis of simultaneously switching inductively and capacitively coupled interconnects driven by CMOS gate

This paper deals in waveform analysis, crosstalk peak and delay estimation of a CMOS gate driven capacitively and inductively coupled interconnect for simultaneously switching inputs. A transmission line based coupled model of interconnect is used for analysis. Peaks and delays at far-end of victim line are estimated for the conditions when the inputs to two coupled interconnects are switching in-phase and out-of-phase. Waveforms are analyzed in general with homogeneous and non-homogeneous drivers for unipolar inputs. Alpha Power Law model of MOS-transistor is used to represent the transistors in CMOS-driver. The comparison of analytically obtained results with SPICE simulations show that the proposed model captures noise peak and their timing; 90% propagation delay; transition time delay and waveform shape with good accuracy.