A Voltage Mode Memristor Bridge Synaptic Circuit with Memristor Emulators

被引:53
作者
Sah, Maheshwar Pd. [1 ]
Yang, Changju [1 ]
Kim, Hyongsuk [1 ]
Chua, Leon [2 ]
机构
[1] Chonbuk Natl Univ, Div Elect & Informat Engn, Jeonju 561756, South Korea
[2] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
基金
新加坡国家研究基金会;
关键词
memristor bridge; non-volatile programming weight; neuron; synapse; synaptic multiplication; CELLULAR NEURAL-NETWORKS; CHIP;
D O I
10.3390/s120303587
中图分类号
O65 [分析化学];
学科分类号
070302 ; 081704 ;
摘要
A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.
引用
收藏
页码:3587 / 3604
页数:18
相关论文
共 28 条
[1]   Hebbian Learning in Spiking Neural Networks With Nanocrystalline Silicon TFTs and Memristive Synapses [J].
Cantley, Kurtis D. ;
Subramaniam, Anand ;
Stiegler, Harvey J. ;
Chapman, Richard A. ;
Vogel, Eric M. .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2011, 10 (05) :1066-1073
[2]   CELLULAR NEURAL NETWORKS - APPLICATIONS [J].
CHUA, LO ;
YANG, L .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1988, 35 (10) :1273-1290
[3]   CELLULAR NEURAL NETWORKS - THEORY [J].
CHUA, LO ;
YANG, L .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1988, 35 (10) :1257-1272
[4]   MEMRISTIVE DEVICES AND SYSTEMS [J].
CHUA, LO ;
KANG, SM .
PROCEEDINGS OF THE IEEE, 1976, 64 (02) :209-223
[5]   MEMRISTOR - MISSING CIRCUIT ELEMENT [J].
CHUA, LO .
IEEE TRANSACTIONS ON CIRCUIT THEORY, 1971, CT18 (05) :507-+
[6]  
Cross SS., 1995, LANCET, V346, P1075, DOI [DOI 10.1016/S0140-6736, DOI 10.1016/S0140-6736(95)91746-2]
[7]   Circuit Elements With Memory: Memristors, Memcapacitors, and Meminductors [J].
Di Ventra, Massimiliano ;
Pershin, Yuriy V. ;
Chua, Leon O. .
PROCEEDINGS OF THE IEEE, 2009, 97 (10) :1717-1724
[8]   A 0.8-mu m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage [J].
DominguezCastro, R ;
Espejo, S ;
RodriguezVazquez, A ;
Carmona, RA ;
Foldesy, P ;
Zarandy, A ;
Szolgay, P ;
Sziranyi, T ;
Roska, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (07) :1013-1026
[9]  
Haykin S., 1999, Neural Networks: A Comprehensive Foundation, DOI DOI 10.1017/S0269888998214044
[10]  
Holler M., 1989, Proceedings of the International Joint Conference on Neural Networks(IJCNN89), V2, P191