AdapNoC: A Fast and Flexible FPGA-based NoC Simulator

Network on Chip (NoC) is the most common interconnection platform for multiprocessor systems-on-chips (MPSoCs). In order to explore the design space of this platform, we need a high-speed, cycle-accurate, and flexible simulation tool. In this paper, we present AdapNoC, a configurable cycle-accurate FPGA-based NoC simulator, which can be configured via software. A wide range of parameters are configurable in FPGA side of the proposed simulator, and the software side is implemented on an embedded soft-core processor. We transfer some parts of simulator, such as Traffic Generators (TGs) and Traffic Receptors (TRs), to software side without any degradation in simulation speed. Moreover, we implement a dual-clock architecture as an innovation in virtualization methodology, which is also capable to share idle time-slots, which helps not only simulate bigger NoCs, but also reduce simulation time drastically. Also, by employing a traffic aggregator architecture, AdapNoC provides table-based adaptive routing algorithm as a configurable parameter in router microarchitecture. We evaluate simulation time of AdapNoC by using Xilinx Virtex-6 XC6VLX240T, and demonstrate 53x-180x speed-up against BOOKSIM. Also, due to our proposed virtualization, and TGs and TRs migration to software side, we can implement a 64-node non-virtualized or a 1024-node virtualized mesh network in only %72 of Xilinx Virtex-6 XC6VLX240T resources.