Application of deterministic logic BIST on industrial circuits

被引：60

作者：

Kiefer, G ^{[1
]}

Vranken, H ^{[1
]}

Marinissen, EJ ^{[1
]}

Wunderlich, HJ ^{[1
]}

机构：

[1] Univ Stuttgart, Comp Architecture Lab, D-70565 Stuttgart, Germany

来源：

INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/TEST.2000.894197

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

We present the application of a deterministic logic BIST scheme on state-of-the-art industrial circuits. Experimental results show that complete fault coverage can be achieved for industrial circuits up to 100K gates with 10,000 test patterns, at a total area cost for BIST hardware of typically 5%-15%. It is demonstrated that a tradeoff is possible between test quality, test time, and silicon area. In contrast to BIST schemes based on test point insertion no modifications of the circuit under test are required complete fault efficiency is guaranteed, and the impact on the design process is minimized.

引用

页码：105 / 114

页数：10

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