Significance-Driven Logic Compression for Energy-Efficient Multiplier Design

被引:21
作者
Qiqieh, Issa [1 ]
Shafik, Rishad [1 ]
Tarawneh, Ghaith [1 ]
Sokolov, Danil [1 ]
Das, Shidhartha [2 ]
Yakovlev, Alex [1 ]
机构
[1] Newcastle Univ, Sch Elect & Elect Engn, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England
[2] ARM, Cambridge CB1 9NJ, England
基金
英国工程与自然科学研究理事会;
关键词
Parallel multipliers; approximate arithmetic; adaptive computing; power-constrained computing; LOW-POWER; APPROXIMATE; PARADIGM;
D O I
10.1109/JETCAS.2018.2846410
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Approximate arithmetic has recently emerged as a promising paradigm for many imprecision-tolerant applications. It can offer substantial reductions in circuit complexity, delay, and energy consumption by relaxing accuracy requirements. In this paper, we propose a novel energy-efficient approximate multiplier design using a significance-driven logic compression (SDLC) approach. Fundamental to this approach is an algorithmic and configurable lossy compression of the partial product rows based on their progressive bit significance. This is followed by the commutative remapping of the resulting product terms to reduce the number of product rows. As such, the complexity of the multiplier in terms of logic cell counts and lengths of critical paths is drastically reduced. A number of multipliers with different hit-widths (4-bit to 128-bit) are designed in System Verilog and synthesized using Synopsys Design Compiler. Post-synthesis experiments showed that up to an order of magnitude energy savings, and reductions of 65% in critical delay, and almost 45% in silicon area can be achieved for an 128-bit multiplier, compared with an accurate equivalent. These gains are achieved with low accuracy losses estimated at less than 0.0028 mean relative error. Additionally, we demonstrate the performance-energy-quality tradeoffs for different degrees of compression, achieved through configurable logic clustering. While evaluating the effectiveness of the proposed approach three case studies were set up. First, a Gaussian blur filter was designed, which demonstrated up to 80% energy reduction with a meagre loss of image quality. Second, we evaluate our approach in machine learning application using perceptron classifier, showed up to 74% energy reduction with negligible error rate. Third, the proposed multiplier designs were used in a power-constrained image processing application. We showed that SDLC can achieve 60x improvement in computation capability, with potential to be employed in ubiquitous systems.
引用
收藏
页码:417 / 430
页数:14
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