Board- and Rack-scale optical interconnection architectures for disaggregated Data Centers

被引:3
作者
Terzenidis, N. [1 ,3 ]
Moralis-Pegios, M. [1 ,3 ]
Pitris, S. [1 ,3 ]
Mourgias-Alexandris, G. [1 ,3 ]
Mitsolidou, C. [1 ,3 ]
Fotiadis, K. [1 ,3 ]
Vyrsokinos, K. [2 ,3 ]
Alexoudi, T. [1 ,3 ]
Pleros, N. [1 ,3 ]
机构
[1] Aristotle Univ Thessaloniki, Dept Informat, Thessaloniki, Greece
[2] Aristotle Univ Thessaloniki, Dept Phys, Thessaloniki, Greece
[3] Aristotle Univ Thessaloniki, Ctr Interdisciplinary Res & Innovat, Thessaloniki, Greece
来源
OPTICAL INTERCONNECTS XX | 2020年 / 11286卷
基金
欧盟地平线“2020”;
关键词
resource disaggregation; optical interconnects; optical switch architecture; disaggregated data centers; AWGR; multi-socket boards; HIGH-PORT;
D O I
10.1117/12.2543166
中图分类号
O43 [光学];
学科分类号
070207 ; 0803 ;
摘要
The ever-increasing energy consumption of Data Centers (DC), along with the significant waste of resources that is observed in traditional DCs, have forced DC operators to invest in solutions that will considerably improve energy efficiency. In this context, Rack- and board-scale resource disaggregation is under heavy research, as a groundbreaking innovation that could amortize the energy and cost impact caused by the vast diversity in resource demand of emerging DC workloads. However disaggregation, by breaking apart the critical CPU-to-memory path, introduces a challenging set of requirements in the underlying network infrastructure, that has to support low-latency and high-throughput communication for a high number of nodes. In this paper we present our recent work on optical interconnects towards enabling resource disaggregation both on Rack-level as well as on board-level. To this end, we have demonstrated the Hipo lambda aos architecture that can efficiently integrate Spanke-based switching with AWGR-based wavelength routing and optical feedforward buffering into high-port switch layouts. The proof-of-concept Hipo lambda aos prototype, based on the 1024-port layout, provide latency performance of 456ns, while system level evaluations reveal sub-mu s latency performance for a variety of synthetic traffic profiles. Moving towards high-capacity board-level interconnects, we present the latest achievements realized within the context of H2020-STREAMS project, where single-mode optical PCBs hosting Si-based routing modules and mid-board optics are exploited towards a massive any-to-any, buffer-less, collision-less and extremely low latency routing platform with 25.6Tb/s throughput. Finally, we combine the Hipolaos and STREAMS architectures in a dual-layer switching scheme and evaluate its performance via system-level simulations.
引用
收藏
页数:7
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