Architecting efficient interconnects for large caches with CACTI 6.0

被引：54

作者：

Muralimanohar, Naveen ^{[1
]}

Balasubramonian, Rajeev ^{[2
]}

Jouppi, Norman P.

机构：

[1] Univ Utah, Salt Lake City, UT 84112 USA

[2] Univ Utah, Sch Computing, Salt Lake City, UT 84112 USA

来源：

IEEE MICRO | 2008年 / 28卷 / 01期

基金：

美国国家科学基金会;

关键词：

Cache design; CACTI; 6.0; On-chip interconnects;

D O I：

10.1109/MM.2008.2

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Interconnects play an increasingly important role in determining the power and performance characteristics of modern processors. An enhanced version of the popular CACTI tool primarily focuses on interconnect design for large scalable caches. The new version can help evaluate novel interconnection networks for cache access and accurately estimate the delay, power, and area of large caches with uniform and nonuniform access times.

引用

页码：69 / 79

页数：11

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