Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level

被引：68

作者：

Das Sharma, Debendra ^{[1
]}

Pasdast, Gerald ^{[1
]}

Qian, Zhiguo ^{[2
]}

Aygun, Kemal ^{[1
]}

机构：

[1] Intel Corp, Santa Clara, CA 95052 USA

[2] Intel Corp, Chandler, AZ 85226 USA

来源：

IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY | 2022年 / 12卷 / 09期

关键词：

Clocks; Packaging; Standards; Protocols; Integrated circuit interconnections; Delays; Training; Accelerator; availability; chiplet; compute express link; co-packaged optics; memory expansion; packaging; Peripheral Component Interconnect (PCI) Express; pooling; power-efficiency; rack scale architecture; reliability;

D O I：

10.1109/TCPMT.2022.3207195

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Universal Chiplet Interconnect Express (UCIe) is an open industry standard interconnect for developing an open chiplet ecosystem, where chiplets from any supplier can be packaged anywhere in an interoperable manner. This article delves into the architectural, circuit, channel, and packaging aspects that we developed that has been adopted in the UCIe 1.0 Specification. We present our results based on our channel and circuit implementation studies.

引用

页码：1423 / 1431

页数：9

共 9 条

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[2] [Anonymous], 2022, Universal Chiplet Interconnect Express (UCIe) Specification Rev 1.0
[3] [Anonymous], 2019, PCI Express Base Specification Revision 5.0 Version 1.0
[4] [Anonymous], 2021, IEEE Electronics Packaging Society Heterogeneous Integration Roadmap
[5] CXL Consortium, 2020, Compute Express Link Specification
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Mahajan, Ravi
Qian, Zhiguo
Viswanath, Ram S.
Srinivasan, Sriram
Aygun, Kemal
Jen, Wei-Lun
Sharan, Sujit
Dhall, Ashish
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Moore, GE
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[8] Nassif Nevine, 2022, 2022 IEEE International Solid- State Circuits Conference (ISSCC), P44, DOI 10.1109/ISSCC42614.2022.9731107
[9] Sharma D. D., 2022, CISC VIS NETW IND GL

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