A ±1.5V CMOS four-quadrant analogue multiplier using 3GHz analogue squaring circuits

被引：0

作者：

Li, SC ^{[1
]}

Lin, KL ^{[1
]}

机构：

[1] Natl Yunlin Univ Sci & Technol, Dept Humam & Sci, ATIS Lab, Touliu 640, Taiwan

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A CMOS four-quadrant analog multiplier using the MOS transistors operated in triode region is proposed. The multiplier is basically constructed by voltage substractors for two differential inputs, and two 3GHz analog squarers for multiplication. Simulation results are given to verify the theoretical analysis. The multiplier has a nonlinearity error less than 1% over +/-1.5V input range. The circuit provides a -3dB bandwidth higher than 1.2GHz and exhibits a THD lower than 4% with a 1.5V peak-to-peak input voltage, which dissipating 249 mu W. The second-order effects including mismatch effects are discussed. The proposed circuit will be useful in analog RF signal-processing applications.

引用

页码：A347 / A350

页数：4

共 44 条

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