Integrated circuit packaging review with an emphasis on 3D packaging

被引:66
作者
Lancaster, Austin [1 ]
Keswani, Manish [1 ]
机构
[1] Univ Arizona, Dept Mat Sci & Engn, Tucson, AZ 85721 USA
关键词
Integrated circuit packaging; 3D packaging; Chip stacking; Package processing; Package functions; THROUGH-SILICON; FLIP-CHIP; COPPER; TECHNOLOGY; CHALLENGES; ELECTRODEPOSITION; INTERCONNECTION; RELIABILITY; DENSITY; NICKEL;
D O I
10.1016/j.vlsi.2017.09.008
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
An introduction to the exciting and continuously growing topic of IC packaging is presented herein. This review starts with a beginner's level introduction to microelectronic packaging and its essential functions. These functions include environmental protection, mechanical stability, thermal management, and electrical connection. Important methods and process techniques for satisfying these essential functions are included. Knowledge of this material is important to understand the history and advancements of packaging technology. The history is reviewed in the context of technology advancement drivers and how they have ultimately led to 3D packaging. 3D packaging is the modern milestone in packaging technology, and it is described in detail. 3D packaging technology poses many advantageous but there are also serious design challenges to "overcome. 3D packaging architecture, advantages, processing, and current challenges become the focus in the second half of this paper.
引用
收藏
页码:204 / 212
页数:9
相关论文
共 105 条
  • [1] Adams J., 2013, PALOMAR TECHNOL
  • [2] Thermo-mechanical challenges in stacked packaging
    Agonafer, Dereje
    Kaisare, Abhijit
    Hossain, Mohammad M.
    Lee, Yongje
    Dewan-Sandur, Bhavani P.
    Dishongh, Terry
    Pekin, Senol
    [J]. HEAT TRANSFER ENGINEERING, 2008, 29 (02) : 134 - 148
  • [3] A review of 3-D packaging technology
    Al-Sarawi, SF
    Abbott, D
    Franzon, PD
    [J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING, 1998, 21 (01): : 2 - 14
  • [4] [Anonymous], 2014, ELECT DESIGN SILICON
  • [5] Vapor Deposition of Highly Conformal Copper Seed Layers for Plating Through-Silicon Vias (TSVs)
    Au, Yeung
    Wang, Qing Min
    Li, Huazhi
    Lehn, Jean-Sebastien M.
    Shenai, Deo V.
    Gordon, Roy G.
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 2012, 159 (06) : D382 - D385
  • [6] Batorfi R, 2011, INT SPR SEM ELECT TE, P112, DOI 10.1109/ISSE.2011.6053561
  • [7] Baumgartner A., 1995, P EL COMP TECHN C
  • [8] THE DIP MAY TAKE ITS FINAL BOWS
    BOWLBY, R
    [J]. IEEE SPECTRUM, 1985, 22 (06) : 37 - 42
  • [9] Buisson T., 2011, 2011 IEEE 13th Electronics Packaging Technology Conference (EPTC 2011), P25, DOI 10.1109/EPTC.2011.6184379
  • [10] Chen A., 2011, HIST BACKGROUNDSEMIC