An on-chip test clock control scheme for multi-clock at-speed testing

To test timing-related faults between synchronous clocks, an at-speed test clock and an automatic test pattern generation scheme are needed However, previous work on designing on-chip at-speed test clock controllers for multi-clock has quadratic increasing area overhead along with linearly increasing clocks. This paper presents a clock-chain based test clock control scheme using an internal phase-locked-loop (PLL) as the at-speed test clock generator, which supports at-speed testing for inter-clock domain and intra-clock domain logic. Experimental results demonstrate that the proposed design has low area overhead when increasing the number of clocks.