A 3.66 μW 12-bit 1 MS/s SAR ADC with mismatch and offset foreground calibration

This paper presents a 12-bit 1 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with foreground calibration for digital-to-analog converter (DAC) mismatch and comparator static offset errors. The proposed foreground calibration utilizes the redundancy to facilitate the detection of DAC weight errors, and compensates for deviations of offset and DAC weights from the ideal value in the analog domain respectively. Benefit from the choice of 0.3 fF unit capacitance, the calibration achieves a 90% reduction in DAC power overhead over the conventional method. The effectiveness of this method is demonstrated by simulations in which differential non-linearity (DNL) is reduced from -1.28 LSB to -0.53 LSB and integral non-linearity (INL) is reduced from 2.20 LSB to 1.08 LSB. The ADC implemented in 40 nm CMOS consumes 3.66 mu W from a 1 V supply, and achieves an improved signal-to-noise and distortion ratio (SNDR) of from 59.68 dB to 66.67 dB and a figure of merit (FoM) of 2.07 fJ/conversion-step at Nyquist rate.