DC and AC performance analysis of 25 nm symmetric/asymmetric double-gate, back-gate and bulk CMOS

被引：10

作者：

Ieong, M ^{[1
]}

Wong, HSP ^{[1
]}

Taur, Y ^{[1
]}

Oldiges, P ^{[1
]}

Frank, D ^{[1
]}

机构：

[1] IBM Corp, SRDC, Hopewell Junction, NY 12533 USA

来源：

2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES | 2000年

关键词：

D O I：

10.1109/SISPAD.2000.871229

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the performance of 25 nm double-gate, back-gate and super-halo CMOS devices has been analyzed including self-consistent 2D quantization effect. The drive current is enhanced by gate-to-body coupling effect for double-gate with ultra-thin body. The channel quantization effect can substantially degrade the drive-current for asymmetric double-gate, back-gate, and bulk CMOSs, It is demonstrated that the exceptional SCE immunity in SDG offers substantial performance leverage over conventional MOSFET structures.

引用

页码：147 / 150

页数：4

共 15 条

[1] FINITE-ELEMENT ANALYSIS OF SEMICONDUCTOR-DEVICES - THE FIELDAY PROGRAM [J].

BUTURLA, EM ;

COTTRELL, PE ;

GROSSMAN, BM ;

SALSBURG, KA .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1981, 25 (04) :218-231

[2]

Fiegna C., 1993, S VLSI TECH, P33

[3]

Frank D. J., 1992, International Electron Devices Meeting 1992. Technical Digest (Cat. No.92CH3211-0), P553, DOI 10.1109/IEDM.1992.307422

[4]

Ghani T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P415, DOI 10.1109/IEDM.1999.824182

[5] A folded-channel MOSFET for deep-sub-tenth micron era [J].

Hisamoto, D ;

Lee, WC ;

Kedzierski, J ;

Anderson, E ;

Takeuchi, H ;

Asano, K ;

King, TJ ;

Bokor, J ;

Hu, CM .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :1032-1034

[6]

Huang X., 1999, IEDM Tech. Dig, P67, DOI DOI 10.1109/IEDM.1999.823848

[7]

IEONG M, UNPUB IEEE EDL

[8]

IEONG M, 1999, 3 NASA WORKSH DEV MO

[9]

Mehrotra M., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P419, DOI 10.1109/IEDM.1999.824183

[10] 25 nm CMOS design considerations [J].

Taur, Y ;

Wann, CH ;

Frank, DJ .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :789-792

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