Fully integrated CMOS frequency synthesizer for ZigBee applications

被引：9

作者：

Singh, SK ^{[1
]}

Bhattacharyya, TK ^{[1
]}

Dutta, A ^{[1
]}

机构：

[1] Indian Inst Technol, Adv VLSI Design Lab, E & ECE Dept, Kharagpur, W Bengal, India

来源：

18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: POWER AWARE DESIGN OF VLSI SYSTEMS | 2005年

关键词：

analog integrated circuits; CMOS RF; frequency synthesizer; phase locked loop; ZigBee;

D O I：

10.1109/ICVD.2005.102

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A single chip ftequency synthesizer compliant, with the ZigBee standard is designed in a standard 0.18mu CMOS process. Integer N topology is chosen for the implementation. Synthesizer consists of third order passive loop filter; a CML based programmable ftequency divider, a standard tristate PFD, a switch on source topology based charge pump and an on chip quadrature VCO. Simulated settling time is 300musec. Synthesizer consumes 22mW of power at supply voltage of 1.8V and occupies an active area of mm(2).

引用

页码：780 / 783

页数：4

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