Very large scale integration architecture for block-matching motion estimation using adaptive rood pattern search algorithm

This study introduces an architecture for motion estimation block of the video encoder using adaptive rood pattern search (ARPS) algorithm. The architecture has been designed for field programmable gate array (FPGA) as well as application specific integrated circuit (ASIC) implementations. Experimental results show that the speed of ARPS algorithm is ahead of several existing fast motion estimation algorithms without compromising the peak signal-to-noise ratio values. The Virtex-4 FPGA implementation of the proposed architecture using Xilinx 14.2 attains a maximum frequency of 103 MHz with <3% usage of slices. ASIC implementation of the proposed architecture with Synopsys design vision tool (0.18 mu m) using 100 MHz frequency involves power consumption of 4.54 mW and occupies 0.073 mm(2). A maximum frequency of 333 MHz has been achieved for the ASIC implementation with 16 x 16 blocks and it can process 651 frames of slow motion video such as Akiyo and 280 frames of fast motion video such as Football of CIF format (352 x 288 resolution) per second. Moreover, the ASIC implementation can process up to 31 frames of HD (1920 x 1080 resolution) video per second. Hence, the proposed architecture fits well in applications such as video conferencing and video phones.