Using SysML for Modelling and Code Generation for Smart Sensor ASICs

The latest developments in networking and the rapidly increasing demand for IoT devices lead to higher demands on time-to-market and production costs. In addition, the complexity of the development processes for smart sensor ASICs is constantly increasing and new methods for automation and code generation are particularly needed in development. This paper describes a new methodology that formalizes functional specification based on SysML and enables automation of Virtual Prototype (VP) development. The virtual prototype is an established approach for early embedded software development. The presented methodology translates natural language written specifications into a modeled and formalized functional specification and enables the generation of behavior descriptions in SystemC that are used for the creation of VP. Furthermore, it enables the connection of the IP-XACT-centric generation of the register interface description, as well as the description of the signal processing parts by MATLAB (R) Simulink (R), with the SysML-based generated functional description.