On ΔΣ fractional-N frequency synthesizers

被引：0

作者：

Zarkeshvari, F ^{[1
]}

Noel, P ^{[1
]}

Kwasniewski, T ^{[1
]}

机构：

[1] Carleton Univ, Dept Elect, Ottawa, ON K1S 5B6, Canada

来源：

ISSCS 2005: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS | 2005年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Delta Sigma fractional-N frequency synthesis achieves low phase noise performance while relaxing the Phase-Locked Loop (PLL) design constraints and reduces the desired channel spacing. This paper reviews the recent advanced techniques on the implementation of fractional-N frequency synthesizers and discusses their advantages and disadvantages. It also addresses the design options and the associated trade-offs.

引用

页码：509 / 512

页数：4

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