Architecture tradeoffs in high-density micro stimulators for retinal prosthesis

被引:48
作者
Sivaprakasam, M [1 ]
Liu, WT
Wang, GX
Weiland, JD
Humayun, MS
机构
[1] Univ Calif Santa Cruz, Dept Elect Engn, Santa Cruz, CA 95064 USA
[2] Univ So Calif, Keck Sch Med, Dept Ophthalmol, Los Angeles, CA 90089 USA
基金
美国国家科学基金会;
关键词
biomedical; functional electrical stimulation (FES); implantable devices; microstimulator; retinal prosthesis;
D O I
10.1109/TCSI.2005.857554
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Electrical stimulation of the retinal layer inside the eye has been identified as a form of visual prosthesis to restore lost vision in blind patients affected by retinitis pigmentosa and age-related macular degeneration, through several studies and experiments. While initial clinical experiments using retinal prosthesis have resulted in visual perception in humans, psychophysical tests and simulations suggest that a high-density retinal prosthesis is required to restore vision to a level of reading and mobility. In the implanted prosthetic device, the microstimulator is functionally the closest to the tissue, delivering the electrical stimulation. Choosing the suitable architecture of the microstimulator requires the knowledge of the available choices and the tradeoffs associated with each of them. This paper presents the different architectures of microstimulator for high-density retinal prosthesis considering both the biomedical and circuit perspectives. The choices for the key aspects of the microstimulator-location of the chip in the eye, electrode configuration, method of stimulation, demultiplexing, stimulation sequence, and communication protocol-are discussed along with the associated tradeoffs for each of them. One of the architectures is used in a prototype microstimulator for an implantable epi-retinal prosthetic device to be used in clinical trials. The chip consists of 60 independently programmable output drivers for delivering electrical stimulus and digital controller for managing run-time and configuration data. The circuit details of the chip fabricated in 1.2-mu m CMOS technology and its measurement results are presented.
引用
收藏
页码:2629 / 2641
页数:13
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