Digit recurrence divider: Optimization and verification

被引：1

作者：

Bessalah, H. ^{[1
]}

Anane, M. ^{[1
]}

Issad, M. ^{[1
]}

Anane, N. ^{[1
]}

Messaoudi, K. ^{[1
]}

机构：

[1] CDTA, Haouch Oukil, Baba Hassen Alg, Algeria

来源：

2007 INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA | 2007年

关键词：

SRT division; high performance design; virtex-II FPGA; double precision computation;

D O I：

10.1109/DTIS.2007.4449495

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we present the Division computation by the SRT algorithm. This last is characterized by the linear convergence. i.e., at each iteration, one quotient digit is obtained as result. Thus, increasing a radix, the iterations number decreases, but the hardware complexity increases which involve the use of a multiplier to calculate the product of quotient digit by the divider. For this purpose and for an implementation on a Xilinx FPGA circuit, we propose for a radix-8 and a maximum redundancy factor, an approach to divert the multiplication. This approach consists of the decomposition of the quotient digits into two terms power of 2. In this way, the multiplication is carried out by shifts and one addition. The implementation results revealed an iteration time of 11,7 ns.

引用

页码：70 / +

页数：2