Real-time FPGA Rectification Implementation Combined with Stereo Camera

被引：0

作者：

Mun, Junwon ^{[1
]}

Kim, Jaeseok ^{[1
]}

机构：

[1] Yonsei Univ, Dept Elect & Elect Engn, Seoul, South Korea

来源：

2015 IEEE INTERNATIONAL SYMPOSIUM ON CONSUMER ELECTRONICS (ISCE) | 2015年

关键词：

Stereo Vision; Rectification; FPGA;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we proposed real-time FPGA-based rectification algorithm implementation combined with stereo camera. Rectification is a necessary pre-required step for stereo matching to align left and right images, including correction of radial distortion. In our experiment, we implemented rectification module in the FPGA combined with stereo camera to verify in video circumstance. As a result, rectification for HD image is processed at 45 fps, with Zynq7020 FPGA.

引用

页数：2