Scalable PD/SOI CMOS with floating bodies

被引：25
|
作者：
Fossum, JG [1 ]
Pelella, MM
Krishnan, S
机构：
[1] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
[2] Adv Micro Devices Inc, Sunnyvale, CA 94008 USA
来源：
IEEE ELECTRON DEVICE LETTERS | 1998年 / 19卷 / 11期
关键词：
CMOS scalability; off-state current; SOI;
D O I：
10.1109/55.728897
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An insightful analysis of the Boating-body (FB) effect on off-state current (I-off) in PD/SOI MOSFET's is done based on simulations calibrated to a published scaled SOI CMOS technology [1], In contrast to the conclusion drawn in [1], the simulations reveal that proven, easily integrated processes for enhancing carrier recombination in the source/drain junction region, in conjunction with normal elevated chip temperature of operation, can effectively suppress the FB-induced increase of I-off, thus enabling exploitation of the unique benefits of scaled PD/SOI CMOS circuits.
引用
收藏
页码：414 / 416
页数：3
相关论文
共 50 条
  • [1] On the performance advantage of PD/SOI CMOS with floating bodies
    Pelella, MM
    Fossum, JG
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (01) : 96 - 104
  • [2] Novel circuit styles for minimization of floating body effects in scaled PD-SOI CMOS
    Das, KK
    Brown, RB
    ISVLSI 2003: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: NEW TRENDS AND TECHNOLOGIES FOR VLSI SYSTEMS DESIGN, 2003, : 29 - 34
  • [3] Optimizing Floating Body Effect & AC performance in 65nm PD-SOI CMOS
    Huang, R. M.
    Chen, T. F.
    Hong, S. F.
    Lin, Y. H.
    Tsai, T. L.
    Liu, E. C.
    Yang, C. W.
    Hsieh, Y. S.
    Huang, Y. T.
    Pelloie, J. -L.
    Tsai, C. T.
    Ma, G. H.
    2007 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 2007, : 93 - +
  • [4] A Floating-Body Dynamic Supply Boosting Technique for Low-Voltage PD/SOI CMOS SRAM
    Joshi, Rajiv
    Kanj, Rouwaida
    Kim, Keunwoo
    Williams, Richard
    Chuang, Ching-Te
    ISLPED'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2007, : 8 - 13
  • [5] Floating body effects in partially-depleted SOI CMOS circuits
    Lu, PF
    Ji, J
    Chuang, CT
    Wagner, LF
    Hsieh, CM
    Kuang, JB
    Hsu, L
    Pelella, MM
    Chu, S
    Anderson, CJ
    1996 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN - DIGEST OF TECHNICAL PAPERS, 1996, : 139 - 144
  • [6] Floating-body effects in partially depleted SOI CMOS circuits
    Lu, PE
    Chuang, CT
    Ji, J
    Wagner, LF
    Hsieh, CM
    Kuang, JB
    Hsu, LLC
    Pelella, MM
    Chu, SFS
    Anderson, CJ
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (08) : 1241 - 1253
  • [7] Floating-body effects on propagation delay in SOI/CMOS LSIs
    Ueda, K
    Morinaka, H
    Yamaguchi, Y
    Iwamatsu, T
    Kim, IJ
    Inoue, Y
    Mashiko, K
    Sumi, T
    1996 IEEE INTERNATIONAL SOI CONFERENCE PROCEEDINGS, 1996, : 142 - 143
  • [8] Integrated Scalable and Tunable RF CMOS SOI Quadrature Hybrid Coupler
    Knopik, Vincent
    Moret, Boris
    Kerherve, Eric
    2017 12TH EUROPEAN MICROWAVE INTEGRATED CIRCUITS CONFERENCE (EUMIC), 2017, : 159 - 162
  • [9] TDBC SOI technology to suppress floating body effect in PD SOI p-MOSFETs
    Luo, Jiexin
    Chen, Jing
    Wu, Qingqing
    Chai, Zhan
    Yu, Tao
    Wang, Xi
    ELECTRONICS LETTERS, 2012, 48 (11) : 652 - 653
  • [10] Performance analysis of tapered gate in PD/SOI CMOS technology
    Hwang, W
    Chuang, CT
    Curran, BW
    Rosenfield, MG
    2001 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2001, : 287 - 290
12345