Implementation of a linear histogram BIST for ADCs

被引：43

作者：

Azaïs, F ^{[1
]}

Bernard, S ^{[1
]}

Bertrand, Y ^{[1
]}

Renovell, M ^{[1
]}

机构：

[1] Univ Montpellier 2, LIRMM, F-34392 Montpellier, France

来源：

DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/DATE.2001.915083

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper validates a linear histogram BIST scheme for ADC resting. This scheme uses a time decomposition technique in order to minimize the required hardware circuitry. A practical implementation is described and the structure together with the operating mode of the different modules are detailed. Through this practical implementation, the performances and limitations of the proposed scheme are evaluated both in terms of additional circuitry and test time.

引用

页码：590 / 595

页数：6

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