Ultimate vertical gate-all-around metal-oxide-semiconductor field-effect transistor and its three-dimensional integrated circuits

被引:31
作者
Ye, Shujun [1 ]
Yamabe, Kikuo [1 ]
Endoh, Tetsuo [1 ,2 ]
机构
[1] Tohoku Univ, Ctr Innovat Integrated Elect Syst, Sendai, Miyagi 9800845, Japan
[2] Tohoku Univ, Grad Sch Engn, Sendai, Miyagi 9808579, Japan
关键词
Gate-all-around; Surrounding-gate; Three-dimensional integrated circuit; MOSFET; CMOS; SRAM; SILICON NANOWIRE TRANSISTORS; PERFORMANCE;
D O I
10.1016/j.mssp.2021.106046
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
According to the International Roadmap for Devices and Systems, gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) will become the main devices in integrated circuits over the next few decades. However, both vertical and lateral GAA-MOSFETs currently face two issues: large variance in sub-10-nm devices and challenges in integration. In particular, vertical GAA-MOSFETs have an asymmetric source/drain structure that is different from that of all other MOSFETs, resulting in unfavorable electrical characteristics. The traditional fabrication process of GAA-MOSFETs is likely the main cause of the above problems, preventing the application of traditional GAA-MOSFETs in integrated circuits. In this work, a novel method is proposed to fabricate the ultimate vertical GAA (UVGAA) MOSFET that may exhibit a symmetric source/drain structure, significantly reduced variance, high yield, high integration, high performance (high speed and low energy consumption), and low cost. Furthermore, a new architecture consisting of a threedimensional (3D) integrated circuit based on the proposed UVGAA-MOSFETs where memory cells and/or logic devices are stacked in the vertical direction is developed. This work paves the way for next-generation integrated circuits with a new 3D architecture.
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页数:10
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