Simulations and electrical testing of superconducting fault current limiter prototypes

The Superconducting Fault Current Limiter (SFCL) is a device of particular interest to electricity companies since it is aimed to maintain fault current levels on electricity networks to acceptable values, i.e. within electrical component design limits. The use of high temperature superconductors (HTS) allows the fabrication of effective SFCL devices with different configurations. In this work, we report on simulations and electrical testing of resistive-type SFCL prototypes. Short-circuit testing of several HTS windings has been carried out at CESI facility. Prospective symmetrical and asymmetrical fault currents 40 times larger than the nominal current value have been applied for 40-160 ms on single-phase devices. As a result, the prospective peak short-circuit current of 4,5 kA has been effectively reduced to 300 A-800 A depending of applied voltage. Time evolution of limited current, voltage across SFCL prototypes, dissipated energy and heating phenomena are reported and discussed.