ATPG-Guided Fault Injection Attacks on Logic Locking

被引:8
作者
Jain, Ayush [1 ]
Rahman, M. Tanjidur [2 ]
Guin, Ujjwal [1 ]
机构
[1] Auburn Univ, Dept Elect & Comp Engn, Auburn, AL 36849 USA
[2] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
来源
PROCEEDINGS OF THE 2020 IEEE INTERNATIONAL CONFERENCE ON PHYSICAL ASSURANCE AND INSPECTION ON ELECTRONICS (PAINE) | 2020年
基金
美国国家科学基金会;
关键词
Logic locking; differential fault analysis; fault injection; IP Piracy; IC overproduction; ENDING PIRACY;
D O I
10.1109/PAINE49178.2020.9337734
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Logic Locking is a well-accepted protection technique to enable trust in the outsourced design and fabrication processes of integrated circuits (ICs) where the original design is modified by incorporating additional key gates in the netlist, resulting in a key-dependent functional circuit. The original functionality of the chip is recovered once it is programmed with the secret key, otherwise, it produces incorrect results for some input patterns. Over the past decade, different attacks have been proposed to break logic locking, simultaneously motivating researchers to develop more secure countermeasures. In this paper, we propose a novel stuck-at fault-based differential fault analysis (DFA) attack, which can be used to break logic locking that relies on a stored secret key. This proposed attack is based on self-referencing, where the secret key is determined by injecting faults in the key lines and comparing the response with its fault-free counterpart. A commercial ATPG tool can be used to generate test patterns that detect these faults, which will be used in DFA to determine the secret key. One test pattern is sufficient to determine one key bit, which results in at most |K| test patterns to determine the entire secret key of size |K|. The proposed attack is generic and can be extended to break any logic locked circuits.
引用
收藏
页数:6
相关论文
共 44 条
  • [1] Alam Md Mahbub, 2019, 2019 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC). Proceedings, P48, DOI 10.1109/FDTC.2019.00015
  • [2] Alkabani YM, 2007, USENIX ASSOCIATION PROCEEDINGS OF THE 16TH USENIX SECURITY SYMPOSIUM, P291
  • [3] [Anonymous], 2017, Synopsys Design Compiler
  • [4] [Anonymous], 2017, TETRAMAX ATPG AUT TE
  • [5] Bryan D, 1985, ISCAS 85 BENCHMARK C
  • [6] Bushnell M., 2004, ESSENTIALS ELECT TES
  • [7] IPP@HDL: Efficient intellectual property protection scheme for IP cores
    Castillo, Encarnacion
    Meyer-Baese, Uwe
    Garcia, Antonio
    Parrilla, Luis
    Lloris, Antonio
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 15 (05) : 578 - 591
  • [8] Champeix C, 2015, INT SYM DEFEC FAU TO, P177, DOI 10.1109/DFT.2015.7315158
  • [9] Hierarchical watermarking in IC design
    Charbon, E
    [J]. IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS, 1998, : 295 - 298
  • [10] Chiang H.-Y., 2019, Transactions on Computer-Aided Design of Integrated Circuits and Systems