Electrical Characterization of High Performance Fine Pitch Interconnects in Silicon-Interconnect Fabric

被引:32
作者
Jangam, SivaChandra [1 ]
Bajwa, Adeel [1 ]
Thankappan, Kannan K. [1 ]
Kittur, Premsagar [1 ]
Iyer, Subramanian S. [1 ]
机构
[1] Univ Calif Los Angeles, Elect Engn Dept, Ctr Heterogeneous Integrat & Performance Scaling, Los Angeles, CA 90024 USA
来源
2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018) | 2018年
关键词
Silicon-Interconnect Fabric; Fine Pitch Interconnects; SuperCHIPS; S-PARAMETER;
D O I
10.1109/ECTC.2018.00197
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The Silicon-Interconnect Fabric (Si-IF) is a highly scalable platform for heterogenous integration of dielets using a fine interconnect pitch (<= 10 mu m) and small inter-dielet spacing (<= 100 mu m) [1]. In our fine-pitch integration scheme, short links on Si-IF (<= 500 mu m) are used for inter-dielet communication, reducing the latency (<= 35 ps) and energy /bit (<= 0.04 pJ/b) [2]. In this paper, we demonstrate the excellent transfer characteristics of the Si-IF links, verified experimentally. The measured insertion loss in these short Si-IF links (<= 500 mu m) is <= 2 dB for frequencies up to 30 GHz. Further, the transfer characteristics show only a single pole, demonstrating an RC-link behavior. We show that assemblies on Si-IF have 16-25X lower parasitic inductance, and 6-40X lower parasitic capacitance compared to assemblies on interposers and PCBs. We illustrate that using the Simple Universal Parallel intERface for chips (SuperCHIPS) protocol [2] for data transfer, data rates of >= 10 Gbps/link are realizable at an energy/bit of <= 0.04 pJ/b. Subsequently, due to the high interconnect density, the overall bandwidth/mm is >= 8 Tbps/mm. This corresponds to an improvement of 120-300X in bandwidth/mm and a reduction of 100-500X in energy/bit compared to a conventional PCB-based integration.
引用
收藏
页码:1283 / 1288
页数:6
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