Simulation based design for back-side illuminated ultrahigh-speed CCDs

A structure for backside illuminated ultrahigh-speed charge coupled devices (CCDs) designed to improve the light sensitivity was investigated. The structure's shooting speed of 1 million frames/second was made possible by directly connecting CCD memories, which record video images, to the photodiodes of individual pixels. The simultaneous parallel recording operation of all pixels results in the highest possible frame rate. Because back-side illumination enables a fill factor of 100 % and a quantum efficiency of 60 %, sensitivity ten or more times that of front-side illumination can be achieved. Applying backside illumination to ultrahigh-speed CCDs can thus solve the problem of a lack of incident light. An n- epitaxial layer/p- epitaxial layer/p+ substrate structure was created to collect electrons generated at the back side traveling to the collection gate. When a photon reaches the deep position near the CCD memory in the p-well, an electron generated by photoelectric conversion directly mixes into the CCD memory. This mixing creates noise, making it necessary to reduce the reach of the incident light. Setting the thickness of a double epitaxial layer to 30 mu m, however, will inhibit the generation of this noise. A potential profile for the n-/p-/p+ structure was calculated using a three-dimensional semiconductor device simulator. The transit time from electron generation to arrival at the collection gate was also calculated. The concentrations of the n- and p- epitaxial layers were optimized to minimize transit time, which was ultimately 1.5 ns. This value is adaptive to a frame rate of 100 million frames/second. Charge transfer simulation of a part of the pixel was conducted to confirm the smooth transfer of electrons without their staying too long in one place.