The DCU: the detector control unit for SPICA-SAFARI

被引:1
作者
Clenet, Antoine [1 ,2 ]
Ravera, Laurent [1 ,2 ]
Bertrand, Bernard [1 ,2 ]
den Hartog, Roland H. [3 ]
Jackson, Brian D. [4 ]
van Leeuven, Bert-Joost [3 ]
van Loon, Dennis [3 ]
Parot, Yann [1 ,2 ]
Pointecouteau, Etienne [1 ,2 ]
Sournac, Anthony [1 ,2 ]
机构
[1] Univ Toulouse, IRAP, UPS OMP, Toulouse, France
[2] CNRS, IRAP, F-31028 Toulouse 4, France
[3] SRON, NL-3584 CA Utrecht, Netherlands
[4] SRON, NL-9747 AD Groningen, Netherlands
来源
SPACE TELESCOPES AND INSTRUMENTATION 2014: OPTICAL, INFRARED, AND MILLIMETER WAVE | 2014年 / 9143卷
关键词
Readout electronics; frequency domain multiplexing;
D O I
10.1117/12.2055740
中图分类号
P1 [天文学];
学科分类号
0704 ;
摘要
TRAP is developing the warm electronic, so called "Detector Control Unit" (DCU), in charge of the readout of the SPICA-SAFARI's TES type detectors. The architecture of the electronics used to readout the 3 500 sensors of the 3 focal plane arrays is based on the frequency domain multiplexing technique (FDM). In each of the 24 detection channels the data of up to 160 pixels are multiplexed in frequency domain between 1 and 3.3 MHz. The DCU provides the AC signals to voltage-bias the detectors; it demodulates the detectors data which are readout in the cold by a SQUID; and it computes a feedback signal for the SQUID to linearize the detection chain in order to optimize its dynamic range. The feedback is computed with a specific technique, so called baseband feedback (BBFB) which ensures that the loop is stable even with long propagation and processing delays (i.e. several mu s) and with fast signals (i.e. frequency carriers at 3.3 MHz). This digital signal processing is complex and has to be done at the same time for the 3 500 pixels. It thus requires an optimisation of the power consumption. We took the advantage of the relatively reduced science signal bandwidth (i.e. 20 - 40 Hz) to decouple the signal sampling frequency (10 MHz) and the data processing rate. Thanks to this method we managed to reduce the total number of operations per second and thus the power consumption of the digital processing circuit by a factor of 10. Moreover we used time multiplexing techniques to share the ressources of the circuit (e.g. a single BBFB module processes 32 pixels). The current version of the firmware is under validation in a Xilinx Virtex 5 FPGA, the final version will be developed in a space qualified digital ASIC. Beyond the firmware architecture the optimization of the instrument concerns the characterization routines and the definition of the optimal parameters. Indeed the operation of the detection and readout chains requires to properly define more than 17 500 parameters (about 5 parameters per pixel). Thus it is mandatory to work out an automatic procedure to set up these optimal values. We defined a fast algorithm which characterizes the phase correction to be applied by the BBFB firmware and the pixel resonance frequencies. We also defined a technique to define the AC-carrier initial phases in such a way that the amplitude of their sum is minimized (for a better use of the DAC dynamic range).
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页数:8
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