Challenges and opportunities in high-k gate dielectric technology

被引：0

作者：

Niwa, M ^{[1
]}

Harada, Y ^{[1
]}

Yamamoto, K ^{[1
]}

Hayashi, S ^{[1
]}

Mitsuhashi, R ^{[1
]}

Eriguchi, K ^{[1
]}

Kubota, M ^{[1
]}

Hoshino, Y ^{[1
]}

Kido, Y ^{[1
]}

Kwong, DL ^{[1
]}

机构：

[1] Matsushita Elect Ind Co Ltd, Semicond Co, ULSI Proc Technol Dev Ctr, Minami Ku, Kyoto 6018413, Japan

来源：

RAPID THERMAL AND OTHER SHORT-TIME PROCESSING TECHNOLOGIES III, PROCEEDINGS | 2002年 / 2002卷 / 11期

关键词：

D O I：

暂无

中图分类号：

O414.1 [热力学];

学科分类号：

摘要：

Thermal stability for two kinds of CVD-HfO2 film prepared by different precursors was investigated clarifying that a control of the inter-diffusion of Hf and Si in the film can lead to thinner equivalent oxide thickness(EOT), lower Jg and higher thermal stability. Also, we successfully demonstrated that the electrical interfacial thickness, hence capacitance equivalent thickness(CET) of the total HfO2 gate stack system can be minimized by means of pre-deposition of metal Hf prior to PVD-HfO2 deposition. In addition, R&D activities as well as some topics for high-k gate dielectrics in Japan have been introduced. Combined with other important technology such as metal gate electrodes, approaches for high-k gate dielectric technology require a partnership between the industry, universities and research institutes on an international scale.

引用

页码：99 / 115

页数：17

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