Performance Analysis of Carbon Nanotube Field Effect Transistor based Digital Circuits

This paper analyzes the performance of CNTFET to check how capable it is, as a future alternative of CMOS technology. Several circuits are simulated which includes 4-to-2 bit Priority Encoder, Full Adder and Full Subtractor using CNTFET HSPICE model and whole process is repeated for CMOS HSPICE model, where CMOS model is used as reference, chosen because it is the existing technology. The main parameter adopted for comparison is Power-Delay Product. Values from the model of CMOS are compared to CNTFET model to check for the suitability of CNTFET as the future of transistor industry. Through the use of simulated results obtained, the work quantitatively shows how promising CNTFET can be, as it exhibits very good Power-Delay Product (PDP) characteristics compared to CMOS technology.