Bounding the Worst-Case Execution Time of Static NUCA Caches

被引：0

作者：

Ding, Yiqiang ^{[1
]}

Zhang, Wei ^{[1
]}

机构：

[1] Virginia Commonwealth Univ, Dept Elect & Comp Engn, Richmond, VA 23284 USA

来源：

2014 IEEE INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2014 IEEE 6TH INTL SYMP ON CYBERSPACE SAFETY AND SECURITY, 2014 IEEE 11TH INTL CONF ON EMBEDDED SOFTWARE AND SYST (HPCC,CSS,ICESS) | 2014年

关键词：

D O I：

10.1109/HPCC.2014.193

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Large on-chip caches with uniform access time are inefficient to be used in multicore processors due to the increasing wire delays across the chip. The Non-Uniform Cache Architecture (NUCA) is proved to be effective to solve the problem of the increasing wire delays in multicore processors. For real-time systems that use multicore processors, it is crucial to bound the worst-case execution time (WCET) accurately and safely. In this paper, we develop a WCET analysis approach to consider the effects of static NUCA caches on WCET.

引用

页码：1181 / 1184

页数：4