Modeling line edge roughness effects in sub 100 nanometer gate length devices

被引：121

作者：

Oldiges, P ^{[1
]}

Lin, QH ^{[1
]}

Petrillo, K ^{[1
]}

Sanchez, M ^{[1
]}

Ieong, M ^{[1
]}

Hargrove, M ^{[1
]}

机构：

[1] IBM Corp, SRDC, Hopewell Junction, NY 12533 USA

来源：

2000 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES | 2000年

关键词：

D O I：

10.1109/SISPAD.2000.871225

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device "slices" sandwiched together to form an MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters.

引用

页码：131 / 134

页数：4

共 5 条

[1] FINITE-ELEMENT ANALYSIS OF SEMICONDUCTOR-DEVICES - THE FIELDAY PROGRAM [J].