A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

被引：0

作者：

Wang, Dong ^{[1
,2
]}

Luan, Jian ^{[1
]}

Guo, Xuan ^{[1
]}

Zhou, Lei ^{[1
]}

Wu, Danyu ^{[1
]}

Liu, Huasen ^{[1
,2
]}

Ding, Hao ^{[3
]}

Wu, Jin ^{[1
]}

Liu, Xinyu ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

[2] Univ Chinese Acad Sci, Sch Microelect, Beijing 100049, Peoples R China

[3] Airforce Engn Univ, Grad Sch, Xian 710051, Shaanxi, Peoples R China

来源：

ELECTRONICS | 2019年 / 8卷 / 02期

关键词：

folding and interpolating; time-interleaved; analog-to-digital converter; SiGe BiCMOS; self-calibration; INTERLEAVED SAR ADC; TO-DIGITAL CONVERTER; FLASH ADC; TRANSCEIVER; SPEED; CMOS;

D O I：

10.3390/electronics8020253

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 m SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 x 3.6 mm(2), consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

引用

页数：14

共 50 条

[41] An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search [J].

Hu, Boyu ;

Ren, Fengbo ;

Chen, Zuow-Zun ;

Jiang, Xicheng ;

Chang, Mau-Chung Frank .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2016, 63 (10) :934-938

[42] An 8-Bit 0.333-2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS [J].

Li, Dengquan ;

Zhang, Liang ;

Zhu, Zhangming ;

Yang, Yintang .

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2015, 24 (06)

[43] A wideband calibration-free 1.5-GS/s 8-bit analog-to-digital converter with low latency [J].

Jiang, Fan ;

Wu, Danyu ;

Zhou, Lei ;

Huang, Yinkun ;

Wu, Jin ;

Jin, Zhi ;

Liu, Xinyu .

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2014, 81 (01) :341-348

[44] A wideband calibration-free 1.5-GS/s 8-bit analog-to-digital converter with low latency [J].

Fan Jiang ;

Danyu Wu ;

Lei Zhou ;

Yinkun Huang ;

Jin Wu ;

Zhi Jin ;

Xinyu Liu .

Analog Integrated Circuits and Signal Processing, 2014, 81 :341-348

[45] An X-Band 5-Bit Active Phase Shifter Based on a Novel Vector-Sum Technique in 0.18μm SiGe BiCMOS [J].

Li, Zhenrong ;

Qiao, Jia ;

Zhuang, Yiqi .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2021, 68 (06) :1763-1767

[46] A 10 MS/s 8-bit charge-redistribution ADC for hybrid pixel applications in 65 m CMOS [J].

Kishishita, Tetsuichi ;

Hemperek, Tomasz ;

Krueger, Hans ;

Koch, Manuel ;

Germic, Leonard ;

Wermes, Norbert .

NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH SECTION A-ACCELERATORS SPECTROMETERS DETECTORS AND ASSOCIATED EQUIPMENT, 2013, 732 :506-510

[47] A 112Gb/s 4-PAM Transceiver Chipset in 0.18μm SiGe BiCMOS Technology for Optical Communication Systems [J].

Shahramian, Shahriar ;

Lee, Jeffrey ;

Weiner, Joe ;

Aroca, Ricardo ;

Baeyens, Yves ;

Kaneda, Noriaki ;

Chen, Young-Kai .

2015 IEEE COMPOUND SEMICONDUCTOR INTEGRATED CIRCUIT SYMPOSIUM (CSICS), 2015,

[48] A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS [J].

Wang, X. Shawn ;

Jin, Xin ;

Du, Jieqiong ;

Li, Yilei ;

Du, Yuan ;

Wong, Chien-Heng ;

Kuan, Yen-Cheng ;

Chan, Chi-Hang ;

Chang, Mau-Chung Frank .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65 (11) :1534-1538

[49] A 7.65-mW 5-bit 90-nm 1-Gs/s Folded Interpolated ADC Without Calibration [J].

D'Amico, Stefano ;

Cocciolo, Giuseppe ;

Spagnolo, Annachiara ;

De Matteis, Marcello ;

Baschirotto, Andrea .

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, 2014, 63 (02) :295-303

[50] A 4GS/s 8-bit time-interleaved SAR ADC with an energy-efficient architecture in 130 nm CMOS [J].

Solis, Fredy ;

Fernandez Bocco, Alvaro ;

Galetto, Agustin C. ;

Passetti, Leandro ;

Hueda, Mario R. ;

Reyes, Benjamin T. .

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2021, 49 (10) :3171-3185

← 1 2 3 4 5 →