A 5GS/s 8-bit ADC with Self-Calibration in 0.18 μm SiGe BiCMOS Technology

被引：0

作者：

Wang, Dong ^{[1
,2
]}

Luan, Jian ^{[1
]}

Guo, Xuan ^{[1
]}

Zhou, Lei ^{[1
]}

Wu, Danyu ^{[1
]}

Liu, Huasen ^{[1
,2
]}

Ding, Hao ^{[3
]}

Wu, Jin ^{[1
]}

Liu, Xinyu ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

[2] Univ Chinese Acad Sci, Sch Microelect, Beijing 100049, Peoples R China

[3] Airforce Engn Univ, Grad Sch, Xian 710051, Shaanxi, Peoples R China

来源：

ELECTRONICS | 2019年 / 8卷 / 02期

关键词：

folding and interpolating; time-interleaved; analog-to-digital converter; SiGe BiCMOS; self-calibration; INTERLEAVED SAR ADC; TO-DIGITAL CONVERTER; FLASH ADC; TRANSCEIVER; SPEED; CMOS;

D O I：

10.3390/electronics8020253

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 m SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 x 3.6 mm(2), consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

引用

页数：14

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