Impact of on-chip process variations on MCML performance

被引:26
作者
Bruma, S
机构
来源
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年
关键词
D O I
10.1109/SOC.2003.1241479
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The effect of on-chip process variations on MOS Current Mode Logic (MCML) performance is explored. A closed form expression for noise-margin is derived. On-chip process variations are shown to set the lower limit for the power dissipation of an MCML family.
引用
收藏
页码:135 / 140
页数:6
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