Impact of on-chip process variations on MCML performance

被引：26
作者：
Bruma, S
机构：
来源：
IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年
关键词：
D O I：
10.1109/SOC.2003.1241479
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The effect of on-chip process variations on MOS Current Mode Logic (MCML) performance is explored. A closed form expression for noise-margin is derived. On-chip process variations are shown to set the lower limit for the power dissipation of an MCML family.
引用
收藏
页码：135 / 140
页数：6
相关论文
共 12 条
[1]  
ANIS M, 2002, ISCAS, pV113
[2]  
Gray P., 2001, ANAL DESIGN ANALOG I
[3]  
Hill C., 1968, Microelectronics, V1, P16
[4]   STATIC AND DYNAMIC NOISE MARGINS OF LOGIC-CIRCUITS [J].
LOHSTROH, J .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1979, 14 (03) :591-598
[5]   WORST-CASE STATIC NOISE MARGIN CRITERIA FOR LOGIC-CIRCUITS AND THEIR MATHEMATICAL EQUIVALENCE [J].
LOHSTROH, J ;
SEEVINCK, E ;
DEGROOT, J .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (06) :803-807
[6]   A GHz MOS adaptive pipeline technique using MOS current-mode logic [J].
Mizuno, M ;
Yamashina, M ;
Furuta, K ;
Igura, H ;
Abiko, H ;
Okabe, K ;
Ono, A ;
Yamada, H .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (06) :784-791
[7]   MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments [J].
Musicer, JM ;
Rabaey, J .
ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, :102-107
[8]  
*PHIL ED T AN SIM, 1998, PSTAR US GUID
[9]  
Seevinck E., 1991, IEEE J SOLID STATE C, V26
[10]   Conquering noise in deep-submicron digital ICs [J].
Shepard, KL ;
Narayanan, V .
IEEE DESIGN & TEST OF COMPUTERS, 1998, 15 (01) :51-62
12