High-Dimensional Many-Objective Bayesian Optimization for LDE-Aware Analog IC Sizing

With the advancement of complementary metal-oxide-semiconductor (CMOS) technologies, layout-dependent effects (LDEs) become increasingly influential to MOSFET characteristics and in turn analog integrated circuit performance. Early awareness of LDEs before the layout stage gets critical in order to help subsequent layout synthesis meet performance requirements and thus reduce design iteration. In this article, we propose a high-dimensional many-objective Bayesian optimization (HMBO)-based LDE-aware sizing methodology to address such challenges. It can effectively tackle the huge configuration space that is incurred by the increased number of optimization variables for considering the LDEs in addition to the conventional sizing variables. Moreover, our proposed method is able to aim for simultaneously satisfying multiple circuit specifications to identify an optimum design point within the enlarged configuration space. In addition, we propose a performance-driven pattern learning scheme called Gibbs-upper confidence bound (UCB) for better managing the dimension splitting. Our method is compared with several prevalent evolutionary algorithms as well as state-of-the-art Bayesian optimization works designed for analog circuit sizing problems. The experimental results demonstrate the high efficacy of our proposed sizing methodology.