A Simple Series Resistance Extraction Methodology for Advanced CMOS Devices

被引：70

作者：

Campbell, J. P. ^{[1
]}

Cheung, K. P. ^{[1
]}

Suehle, J. S. ^{[1
]}

Oates, A. ^{[2
]}

机构：

[1] NIST, Gaithersburg, MD 20899 USA

[2] Taiwan Semicond Mfg Corp, Hsinchu 30844, Taiwan

来源：

IEEE ELECTRON DEVICE LETTERS | 2011年 / 32卷 / 08期

关键词：

Series resistance; EFFECTIVE CHANNEL-LENGTH; GATE;

D O I：

10.1109/LED.2011.2158183

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Series resistance has become a serious obstacle inhibiting the performance of advanced CMOS devices. However, series resistance quantification in these same advanced CMOS devices is becoming exceedingly difficult. In this letter, we demonstrate a very simple series resistance extraction procedure which is derived only from the ratio of two linear I-D-V-G measurements. This approach has a verifiable accuracy check and is successfully used to extract the series resistance from several advanced devices. Furthermore, the validity of the assumptions used in this series resistance extraction procedure is examined and shown to be justified. In an attempt to further test the validity of this technique, several known external resistors were inserted in series with the device under test. The series resistance extraction procedure faithfully reproduces these known external resistances to within +/- 10%.

引用

页码：1047 / 1049

页数：3

共 15 条

[11] A novel technique to determine the gate and drain bias dependent series resistance in drain engineered MOSFET's using one single device [J].