Design of an Ultra Compact Low Power 60 GHz Frequency Doubler in 22 nm FD-SOI

This paper presents the design and characterization of a 60GHz differential frequency doubler fabricated in a 22nm FD-SOI CMOS technology. The push-push amplifiers are driven by quadrature differential input signals, generated by a two-stage polyphase filter. To compensate for the inherent losses of the polyphase filter a set of two-stage CMOS inverters is implemented. Integrated into a very compact area of 202 mu m x 164 mu m = 0.033 mm(2), the proposed design has achieved -11dBm output power and -10 dB conversion gain with an output -3 dB bandwidth over 16 GHz. While operating at its saturated output power, the circuit only consumes 8mW of DC power from a 0.8V supply, which is to the best knowledge of the authors the lowest reported for active mm-wave frequency doublers, and provides 35 dB of suppression of the fundamental achieved around the center frequency. By increasing the supply voltage to 1 V, the conversion gain and output power can be improved to -5.7 dB and -8.2dBm at a cost of 16mW of DC power.